The invention relates to a method of selecting a signal from among N signals, the selection taking place in that a validation signal associated with the signal to be selected is placed in an active state by means of a selection signal.
U.S. Pat. No. 4,853,653 describes a switching device designed to deliver an output signal selected among N input signals which carries out such a method. In this switching device, the validation signals result from a storage of selection signals associated therewith. If one of the validation signals is in an active state, i.e. at a logic level 1 in the description relating to the known device, the storage of the selection signals associated with the other validation signals is inhibited. This inhibition is only lifted after a given time period has elapsed following the moment at which one of the selection signals, i.e. the one which is associated with the validation signal which is in the active state, enters a passive state, i.e. from the logic level 1 to the logic level 0 in the description relating to the known device. The method used in the known switching device thus introduces a delay into the switching of the signals, i.e. there is a non-negligible time interval during which the output signal of the switching device does not correspond to any of the input signals. This means that the output signal has a zero duty cycle during several consecutive cycles of the relevant signal.
Such a latent period is not acceptable in a number of applications. In particular, if the switching device is used in an apparatus designed to exchange data with a smart card, which apparatus must then provide to the smart card a clock signal selected among N clock signals available in the apparatus, the clock signal provided to the chip card must comply with the provisions of a standard ISO/IEC 7816-3:1997, which requires that the duty cycle of the relevant signal must always lie between 45% and 55%. According to the ISO/IEC 7816-3:1997 standard, only a single breach of this rule is acceptable in the course of one switching operation.
The selection method used in the known switching device will inevitably cause a succession of breaches of this rule on account of the inhibitions described above and is accordingly not compatible with the ISO/IEC 7816-3:1997 standard.
A suppression of the inhibition step would seem to provide a natural solution to this problem, but this generates other difficulties.
Indeed, if the selection signals switch at the same time when an active front commanding the storage of said signals occurs, the next state of the validation signals is unpredictable.
If, for example, the state of the selection signal associated with that one of the validation signals which was previously active has been detected, said validation signal will enter an inactive state. Now, if in this example the switching to the active state of the selection signal associated with the validation signal which should then enter an active state is not detected, owing to the fact that its switching occurs simultaneously with the active front commanding the storage, the associated validation signal will remain in the inactive state. In that case, all validation signals will be in the inactive state until the next active front commanding the storage of the selection signals appears. This will cause the appearance of a latent period during which the output signal of the switching device will twice have a zero duty cycle. Such a method is accordingly not compatible with the ISO/IEC 7816-3:1997 standard, either.